Response Electronics CL6011B Especificações Página 241

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4Ć159FST Configuration
Original Ć June 1990 CE4.2:CL6211
TM TM
97
INSTRUCTION NAME: TM (timer)
DESCRIPTION : This instruction provides a time-out interval for the SVD input. A transition of the
SVD input from the logic 0 to the logic 1 state causes the SVD output to go to the logic 1 state for the
time specified by the time-out value in operand 1, if the reset value in operand 2 is 0. The time-out
value is loaded into an internal register (HA) with each transition of the SVD input from 0 to 1.
Register HA is then decreased with each execution of the function until one of the following occurs:
H The SVD input goes from 0 to 1
H The reset value goes to 1
H Register HA reaches a count of 0
When register HA reaches 0, the SVD output is set to 0. If the reset value is 1, the SVA and SVD
output will be 0.
GRAPHIC REPRESENTATION: SYMBOLIC REPRESENTATION:
1
0
INPUT
0
OUTPUT
t
0
t
1
tt
t
4
32
t
0
t
1
tt
t
4
32
SVD(IN)
OPERAND 2
OPERANDS
t
0
t
2
= OPERAND 1 VALUE
100% OF OPERAND 1
SVA(OUT)
0
t
0
t
1
tt
t
4
32
SVD(OUT)
1
CASE 1
1
0
t
0
t
1
tt
t
4
32
SVD(IN)
OPERAND 2
CASE 2
0
t
0
t
1
tt
t
4
32
100% OF OPERAND 1
SVA(OUT)
1
0
SVD(OUT)
OPERAND 1
OPERAND 2
TM
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